1. Technical Field
The present invention relates to a method of designing a semiconductor device and a method of manufacturing the semiconductor device.
2. Related Art
A via which is connected to an interconnect is required to have electrically low resistance. However, in the related art, there has been a problem that a high-resistivity layer is formed in the via which is electrically connected to a polysilicon-insulator-polysilicon (PIP) capacitor or a metal-insulator-metal (MIM) capacitor configured using polysilicon or metal as an electrode and using an insulating film such as an oxide film or a nitride film as a capacitive film, to thereby cause the conduction failure. However, it is difficult to detect the conduction failure in an inspection after the via formation due to the high resistance of the via. For this reason, it is necessary to design the semiconductor device so that conduction failure of the via is not generated from the beginning.
Japanese Unexamined patent publication NO. 2005-252027 discloses a semiconductor device having a multilayer interconnect structure including a semiconductor substrate; a plurality of metal interconnects provided on the semiconductor substrate and electrically isolated from the upper and lower metal interconnects by an insulating interlayer; and, at least one via passing through the insulating interlayer and connecting a metal interconnect of a first layer and a metal interconnect of a second layer positioned at an upper layer of the metal interconnect of the first layer, wherein potential of a predetermined interconnect of the metal interconnect of the first layer is electrically floated from the semiconductor substrate, and a capacitance value between the metal interconnect of the first layer and the semiconductor substrate per one via provided on the predetermined interconnect of the metal interconnect of the first layer is a predetermined value or less.
However, in the configuration of the related art, there has been a problem that a large number of vias are required, and the chip size becomes large. The inventor has found the configuration of the invention as a result of conducting various studies by taking into consideration that the high-resistivity layer is formed due to the influences such as charges or moisture in a process at the time of opening a via hole, in order to form the via to be electrically connected to the capacitor.